1. Technical Field
The present disclosure relates to a memory device, and more particularly, to a NAND flash memory having a command/address (C/A) pin and a flash memory system including the same.
2. Discussion of the Related Art
Semiconductor memory devices are storage devices for storing data. Semiconductor memory devices can be classified as a random access memory (RAM) and a read only memory (ROM). A RAM is a volatile memory device that requires power to maintain stored data. A ROM is a nonvolatile memory device that can maintain stored data even when not powered.
Examples of RAMs include a dynamic RAM (DRAM) and a static RAM (SRAM). Examples of ROMs include a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory. Examples of flash memories include a NOR flash memory and a NAND flash memory. NAND flash memories are widely used for mobile communication terminals, portable media players, digital cameras, and mobile storage media.
FIG. 1 illustrates a conventional NAND flash memory 100, and FIG. 2 is a table providing descriptions of pins of the NAND flash memory 100. Referring to FIG. 1, the NAND flash memory 100 includes control pins such as RnB, ALE, CLE, nWE, and nCE pins that are formed on a first surface 110 of the NAND flash memory 100. The NAND flash memory 100 further includes data pins such as DQ0 through DQ7 pins formed on a to second surface 120.
The pin structure of the NAND flash memory 100 shown in FIG. 1 is a structure for a thin small outline package (TSOP). However, since the control pins are formed on one surface of the NAND flash memory 100, board structure for the NAND flash memory 100 is complicated. Furthermore, when a memory module is formed using a plurality of NAND flash memories having the pin structure illustrated in FIG. 1, the structure of a printed circuit board (PCB) for the memory module is complicated.
FIG. 3 is a block diagram illustrating a flash memory system 200 having a multi-bank architecture using the NAND flash memory 100 of FIG. 1. Referring to FIG. 3, the flash memory system 200 may include a flash controller 250, first bank 210, second bank 220, third bank 230, and fourth bank 240.
Each of the banks 210, 220, 230, and 240 includes four NAND flash memories. For example, the first bank 210 includes four NAND flash memories 211, 212, 213, and 214. The second bank 220 includes four NAND flash memories 221, 222, 223, and 224. The third bank 230 includes four NAND flash memories 231, 232, 233, and 234. The fourth bank 240 includes four NAND flash memories 241, 242, 243, and 244. The flash controller 250 is connected to the banks 210, 220, 230, and 240 through four channels 1 through 4. Here, each of the channels 1 through 4 connects corresponding NAND flash memories of the banks 210, 220, 230, and 240. For example, channel 1 connects NAND flash memories 211, 221, 231, and 241 of the banks 210, 220, 230, and 240, respectively.
Similarly, channel 2 connects NAND flash memories 212, 222, 232, and 242. Channel 3 connects NAND flash memories 213, 223, 233, and 243. Channel 4 connects NAND flash memories 214, 224, 234, and 244.
The controller 250 performs a bank interleaving operation using chip enable signals nCE0-nCEX (where X is a positive integer). In so doing, the controller 250 receives as many enable signals and read and busy signals RnB0-RnBX as there are NAND flash memories. As used herein, bank interleaving is a data reading or writing operation performed between banks of a memory system in which two or more banks share a common channel. For example, in a bank interleaving operation, the flash controller 250 reads data from and/or writes data to the NAND flash memories 211, 221, 231, and 241 connected to channel 1 while moving between the NAND flash memories 211, 221, 231, and 241.
As described above, as many chip enable signals nCE0 to nCEX and ready and busy signals RnB0 to RnBX are used as the number of flash memory chips for a bank interleaving operation. Therefore, when the flash memory system 200 uses all the four channels 1 to 4, sixteen chip enable signals nCE0 to nCE15 and sixteen read and busy signals RnB0 to RnB15 are used for a bank interleaving operation. Accordingly, the structure of the flash memory system 200 becomes more complicated as the numbers of banks and flash memory chips increase.
A conventional NAND flash memory receives address and command signals through a data input/output (DQ) pin. Therefore, when address and command signals are input to the NAND flash memory, data cannot be input to or output from the NAND flash memory. This results in a data delay time Data input/output is especially delayed when a bank interleaving operation is performed.
Furthermore, when data is written to or read from a cell array of a conventional NAND flash memory, RnB signals are generated. In this case, a flash controller cannot perform any operation until the writing/reading operation is completed. This reduces the performance of a flash memory system.